This CD contains all lecture slides and the lab assignments. Techniques to reduce and tolerate the pipeline effective latency. Linear pipeline processor.
Integration of the predictor in the segmented pipeline. Two-bit predictors with history registers. Jump prediction - concept. Implementation of vector interruptions. The impact of exceptions and interruptions in the segmentation process.
Recovering the rename table in cases of exception. Reorder Buffer integration. Integrating pipeline renaming. Renumbering registers - concept. Recovering Precise State in cases of exception and interruption. Re-order Buffer and Future File technique (Smith & Plezskun, 1985).
Types of multithreading: fine-grain, switch-on-event, simultaneous multithreading. Prerequisites for simultaneously executing two instructions. Fetching multiple instructions within a clock cycle. Control dependencies among memory instructions. Dependence control among registers.
The concept behind specific purpose processors: embedded, DSP, and 3D graphic processors. Memory organisation by vectoral access. Datapath partitioning in lanes. Specific memory access instructions (Strides and Gather/Scatter). Advantages and drawbacks of vectorial execution.
Ability to create and use models of reality. Ability to solve problems through the application of scientific and engineering methods. Use verilog as a hardware modelling language in order to model the processors presented in class. Ability to create a model of the processors presented and simulate their operation. Mastery of LogicWorks 4 and LogicWorks 5 simulators.
Microprocessor Logicworks 5 How To Take Decisions
Initiative: Resolution, knowing how to take decisions and how to act in order to solve a problem. Ability to take take decisions when faced with uncertainty or contradictory requirements. Ability to analyse the process on completion. Know-how to apply the solution cycle to common scientific and engineering problems: specification, coming with ideas and alternatives, design solution strategies, carrying out the strategy, validation, interpretation and evaluation of results.
In other words, students will work in groups and by stages but must assemble all of the processor components to produce a working whole. The processor must include a cache hierarchy (instructions and data), and must share data with a disk controller through a bus and main memory.It should be stressed that all students will work on the same processor. Assume responsibility for one"s own work.Introduction to the architecture of current processors.Theory and Problems: Common problems (lecture)Students will collectively undertake a practical session involving implementing a simple 5, 6, or 7-stage multi-cyclic, superscalar processor incorporating jump prediction. Ability to understand and constructively criticise presentations given by others. Ability to set up and organise either a uni- or multi-disciplinary group to tackle a complex project.
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